Experiment No. : 02
Aim of the Experiment: –
(i) Identification & verification of NOT (7404), AND (7408) OR (7432) & XOR (7486) gates.
(ii) Designing, construction and verification of Binary to Grey convertor and Grey to Binary convertor.
(iii) Design, construction and verification of 3-bit Parity Generator and 4-bit odd parity Checker circuit.
Components Required-
| Sl. No. | Equipment/ Component Name | Specification | Quantity |
|---|---|---|---|
| 1 | NOT gate | IC 7404 | 1 no. |
| 2 | AND gate | IC 7408 | 1 no. |
| 3 | OR gate | IC 7432 | 1 no. |
| 4 | XOR gate | IC 7486 | 1 no. |
| 5 | LED | 1 no. | |
| 6 | Resistor | 330 Ω | 2 nos. |
| 7 | Breadboard | – | 1 no. |
| 8 | DC Power Supply | 5 Volt | 1 no. |
| 9 | Connecting Wires | – | As per required |
| 10 | Slide switch | – | 5 nos. |
Theory-
(i) Identification & verification of NOT (7404), AND (7408) OR (7432) & XOR (7486) gates.
NOT Gate: The NOT gate is called an inverter. The output is high when the input is low. The output is low when the input is high.
Truth Table for NOT Gate:
| Input | Output |
|---|---|
| A | Y=Ā |
| 0 | 1 |
| 1 | 0 |
AND Gate: The output is high when both the inputs are high. The output is low level when any one of the inputs is low.
Truth Table for AND Gate:
| Input | Output | |
| A | B | Y= AB |
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
OR Gate: The output is high when any one of the inputs is high. The output is low level when both the inputs are low.
Truth Table for OR Gate:
| Input | Output | |
| A | B | Y= A + B |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
XOR Gate – An XOR (Exclusive OR) gate gives a HIGH output (1) only when the number of HIGH inputs is odd.
Truth Table for XOR Gate:
| Input | Output | |
| A | B | Y = A ⊕ B |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Circuit Diagram: –
Breadboard Connection of all NOT (7404), AND (7408), OR (7432) & XOR (7486) gates.
Observation Tables for ICs:
Look into Truth Tables for Each gates.
(ii) Designing, construction and verification of Binary to Grey convertor and Grey to Binary convertor.
General Rule for Gray Code Conversion:
- Keep the first (MSB) bit the same as binary.
- For the remaining bits: Gray bit = Binary bit XOR Previous Binary bit Let Bn be binary bits and Gn be Gray code bits.
- G₁ = B₁ (MSB remains same)
- G₂ = B₂ ⊕ B₁
- G₃ = B₃ ⊕ B₂ and so on…
Taking example of 3 Bit Binary to Gray Code Converter
So, the truth table of 3 Bit Binary to Gray Code Converter is given below,
| Binary Code Input | Gray Code Output | ||||
| B2 | B1 | B0 | G2 | G1 | G0 |
| 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 0 | 0 | 1 | 1 |
| 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 1 | 1 | 1 |
| 1 | 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 | 0 |
From table we see that Logic Functions will be for G2 G1 G0 is
G2 = B2,
G1 = B2 ⊕ B1,
G0 = B1 ⊕ B0
Now the Logic Diagram is-
Circuit Diagram: – Breadboard Connection of Binary to Grey code convertor.
General Rule for Gray Code to Binary Conversion:
- Keep the first (MSB) bit the same as binary.
- For remaining bits: Binary bit = Previous Binary bit XOR Current Gray bit Let Gn be Gray bits and Bn be Binary bits.
- B₁ = G₁ (MSB remains same)
- B₂ = B₁ ⊕ G₂
- B₃ = B₂ ⊕ G₃ and so on…
Taking example of 3 bit Gray To Binary Code Converter
So, the truth table of 3 Bit Gray to binary code converter is given below
| Gray Code Input | Binary Code Output | ||||
| G2 | G1 | G0 | B2 | B1 | B0 |
| 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 0 | 0 | 1 | 1 |
| 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 | 1 |
| 1 | 0 | 1 | 1 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 | 0 | 1 |
From table we see that Logic Functions will be for B2 B1 B0 is
B2 = G2
B1 = B2 ⊕ G1
B0 = B1 ⊕ G0
Now the Logic Diagram is-
Circuit Diagram: – Breadboard Connection of Grey code to Binary convertor
(iii) Design, construction and verification of 3-bit Parity Generator and 4-bit parity Checker circuit.
Basic Principle to generate the parity bit is “the module sum of even number of 1’s is 0 and the module sum of odd number of 1’s is 1. Parity Generator generates a bit to pair with the code group so as to make the number of 1’s either odd or even as desired at the transmitter side.
Basic rule for Even/Odd Parity Generator by using XOR gate
The XOR gate is the heart of parity generators because of this fundamental property
XOR of multiple bits is 1 if the number of 1s is odd, and 0 if the number of 1s is even
| Even Parity Generator Rule (using XOR) | Odd Parity Generator Rule (using XOR) |
| For even parity, the total number of 1’s (including the parity bit) must be even. So, Parity Bit = A ⊕ B ⊕ C ⊕ … ⮞ If the result of XOR is 1 (odd number of 1s), parity bit = 1 ⮞ If the result is 0 (even number of 1s), parity bit = 0 | For odd parity, the total number of 1’s (including the parity bit) must be odd. So, Parity Bit = NOT (A ⊕ B ⊕ C ⊕ …) ⮞ If the result of XOR is 1 (odd number of 1s), parity bit = 0 ⮞ If the result is 0 (even number of 1s), parity bit = 1 NOTE- This can be achieved by inverting the output of an even parity generator using a NOT gate |
Taking example of 3 Bit Even/Odd Parity Generator Truth table-
| Input | Output | |||
| X | Y | Z | Peven | Podd |
| 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 |
From table we see that Logic Functions and diagram will be for Peven and Podd
Peven = X⊕Y⊕ Z
Logic Diagram for 3 Bit Even Parity Generator
Podd = ( X⊕Y⊕Z )’
Logic Diagram for 3 Bit Odd Parity Generator
Circuit Diagram: – Breadboard Connection : 3 Bit Even/3 Bit Odd Parity Generator
RED led show even parity system and BLUE led show odd parity system
4 Bit Even/Odd Parity Checker
At Receiver, checks each code group to see that the total number of 1’s (including Parity bit) is consistent with the agreed upon type of Parity (with Transmitter).
Taking example of 4 Bit Even/Odd Parity checker Truth table
| Input Message | Parity Bit | One XOR is extra connected in right side for passing information based on TX-RX | ||||
| X | Y | Z | For Even | For Odd | For Even TX/RX Put Value-1 | For Odd TX/RX Put Value-0 |
| Message passed checked by glowing of LED in each condition | ||||||
| 0 | 0 | 0 | 0 | 1 | ON | ON |
| 0 | 0 | 1 | 1 | 0 | ON | ON |
| 0 | 1 | 0 | 1 | 0 | ON | ON |
| 0 | 1 | 1 | 0 | 1 | ON | ON |
| 1 | 0 | 0 | 1 | 0 | ON | ON |
| 1 | 0 | 1 | 0 | 1 | ON | ON |
| 1 | 1 | 0 | 0 | 1 | ON | ON |
| 1 | 1 | 1 | 1 | 0 | ON | ON |
So, if in even parity checker if message bit including parity bit is odd then LED doesn’t glow also same rule for odd parity checker.
From table we see that Logic Diagram will be for PCHECKER
Circuit Diagram: – Breadboard Connection for 4 Bit Even/Odd Parity Checker.
Procedure: –
- Connect the circuit as shown in the circuit diagram.
- Before switching ON power Supply, make sure that the connections are correct.
- Apply the input logic as per Truth table in terms of +5 volts for state-1 and 0 volts for state-0.
- Observe the Output state.
- Verify the truth table.
- Repeat steps from 3 to 5 for all possible combination.
Precaution: –
- All connections should be made properly.
Result: –
To be Written by Student.