Familiarization with 8051 microcontroller, experimental kits, simulator and programming  environment.

Experiment No.: – 1

Aim of the Experiment: –

Familiarization with 8051 microcontroller, experimental kits, simulator and programming environment.

Features of 8051 Microcontroller: –

In 1981, Intel Corporation introduced an 8051 microcontroller (8-bit).

D7

D6

D5

D4

D3

D2

D1

D0

CPU	RAM	ROM
I/O Port	Timer	Serial COM Port

•ROM – 4K Bytes.

•RAM – 128 Bytes.

•Timers/Counters – 2 nos. (16-Bit)

•I/O port (8-bit) – 4 nos. ( P0-P3)

•Serial port – one.

Registers:-

The most widely used registers of 8051 are A,B,R0-R7,  DPTR(data pointer) and PC(program counter). All are  8-bit except DPTR & PC these two are 16-bit registers.

A

B

R0

R1

R2

R3

R4

R5

R6

R7

DPH	DPL
PC (program counter)

PSW(program status word) register

* It is a 8-bit register & also known as Flag register.

PSW.7	PSW.6	PSW.5	PSW.4	PSW.3	PSW.2	PSW.1	PSW.0
CY	AC	F0	RS1	RS0	OV	—–	P

•CY (the carry flag):- This flag is set whenever there is a carry out from the D7 bit,              after an 8-bit addition or subtraction. It can also set to 1 or 0 directly by an instruction such as ‘SETB C’ (set bit carry) & ‘CLR C’ ( clear carry).

•AC (the auxiliary carry flag):- If there is a carry from D3 to D4 during an ADD or SUB operation, this bit is set otherwise, it is cleared.

•P (the parity flag):- The parity flag reflects the number of 1s in the A(accumulator) register only. if the A register contains an odd number of 1s, then P=1, & P=0,if A has even nos. of 1s.

•OV (the overflow flag):- This flag is set whenever the result of a signed number operation is too large, causing the high-order bit to overflow into the sign bit. It is used only to detect errors in signed arithmetic operation.

8051 REGISTER BANKS: –

RAM memory space are divided as following-

•32 bytes (00-7F)h, for register bank & stack.

•16 bytes (20-2F)h, for bit addressable read/write memory.

•80 bytes (30-7F)h, for read & write storage, also known as scratch pad.

Scratch Pad RAM (30-7F)H

Bit-Addressable RAM (20-2F)H

Register Bank 3 (18-1F)H

Register Bank 2 (10-17)H

Register Bank 1 (Stack) (08-0F)H

Register Bank 0 (00-07)H

32 bytes of RAM are divided into Four register bank such as

     Register Bank 0 (00-07)H,

     Register Bank 1 (08-0F)H,

     Register Bank 2 (10-17)H,

     Register Bank 3 (18-1F)H.

    each bank has 8 register (R0-R7).

Default register bank is Register bank 0.

Register Bank	RS1(PSW.4)	RS0(PSW.3)	Address
Bank 0	0	0	00H-07H
Bank 1	0	1	08H-0FH
Bank 2	1	0	10H-17H
Bank 3	1	1	18H-1FH

Bit Addressable RAM

Special Function Register

Data Memory: –

Pin Diagram: –

INSTRUCTION SETS OF 8051

Data Transfer Instructions

MOV dest, source  dest ß source.

Stack instructions:

PUSH byte  ;increment stack pointer,              

  ;move byte on stack

POP byte     ;move from stack to byte,

                  ;decrement stack pointer

Exchange instructions: –

XCH a, byte  ;exchange accumulator and byte

XCHD a, byte  ;exchange low nibbles of        

  ;accumulator and byte

Arithmetic Instructions

• Add

• Subtract

• Increment

• Decrement

• Multiply

• Divide

• Decimal adjust

Mnemonic	Description
ADD A, byte	add A to byte, put result in A
ADDC A, byte	add with carry
SUBB A, byte	subtract with borrow
INC A	increment A
INC MemAddr	increment byte in memory
INC DPTR	increment data pointer
DEC A	decrement accumulator
DEC byte	decrement byte
MUL AB	multiply accumulator by b register
DIV AB	divide accumulator by b register
DA A	decimal adjust the accumulator

Instructions that Affect PSW bits

Logic Instructions

• Bitwise logic operations (AND, OR, XOR, NOT)

• Clear

• Rotate

• Swap

Logic instructions do NOT affect the flags in PSW

Bitwise Logic

ANL —-> AND

ORL —-> OR

XRL —-> XOR

CPL —-> Complement

Other Logic Instructions

CLR  – clear

RL   – rotate left

RLC  – rotate left through Carry

RR   – rotate right

RRC  – rotate right through Carry

SWAP – swap accumulator nibbles

Program Flow Control

• Unconditional jumps (“go to”)

• Conditional jumps

• Call and return

Unconditional Jumps

SJMP <rel addr>      ; Short jump, relative address is 8-bit 2’s complement number, so jump can be up to 127 locations forward, or 128 locations back.

LJMP <address 16> ; Long jump

AJMP <address 11> ; Absolute jump to anywhere within 2K block of program memory

JMP @A + DPTR           ; Long indexed jump

Conditional jumps

Mnemonic	Description
JZ <rel addr>	Jump if a = 0
JNZ <rel addr>	Jump if a != 0
JC <rel addr>	Jump if C = 1
JNC <rel addr>	Jump if C != 1
JB <bitAddr>, <rel addr>	Jump if bit = 1
JNB <bitAddr>,<rel addr>	Jump if bit != 1
JBC <bitAddr>, <rel addr>	Jump if bit =1,  &clear bit
CJNE A, direct, <rel addr>	Compare A and memory, jump if not equal

Addressing Modes

Immediate Mode – specify data by its value

mov A, #0       ;put 0 in the accumulator

                   ;A = 00000000

mov R4, #11h      ;put 11hex in the R4 register

                     ;R4 = 00010001

mov B, #11        ;put 11 decimal in b register

                     ;B = 00001011

mov DPTR,#7521h  ;put 7521 hex in DPTR

                    ;DPTR = 0111010100100001

Register Addressing – either source or destination is one of CPU register

  MOV R0,A

MOV A,R7

ADD A,R4

ADD A,R7

MOV DPTR,#25F5H

MOV R5,DPL

MOV R,DPH

Note that MOV R4,R7 is incorrect.

Direct Mode – specify data by its 8-bit address

                           Usually for 30h-7Fh of RAM

Mov A, 70h        ; copy contents of RAM at 70h to A

Mov R0,40h       ; copy contents of RAM at 70h to A

Mov 56h,A        ; put contents of a at 56h to A

Mov 0D0h,A         ; put contents of a into PSW

Direct Mode – play with R0-R7 by direct address

MOV A,4  º  MOV A,R4

MOV A,7  º  MOV A,R7

MOV 7,2  º  MOV R7,R2

MOV R2,#5   ;Put 5 in R2

MOV R2,5    ;Put content of RAM at 5 in R2

Register Indirect – the address of the source or destination is specified in registers

Uses registers R0 or R1 for 8-bit address:

mov psw, #0  ; use register bank 0

mov r0, #0x3C 

mov @r0, #3  ; memory at 3C gets #3

  ; M[3C] ß 3

Uses DPTR register for 16-bit addresses:

mov dptr, #0x9000  ; dptr ß 9000h

movx a, @dptr  ; a ß M[9000h]

Note that 9000h is an address in external memory

Register Indexed Mode – source or destination address is the sum of the base address and the accumulator(Index)

Base address can be DPTR or PC

mov dptr, #4000h

mov a, #5

movc a, @a + dptr  ;a ß M[4005]

Register Indexed Mode continue

Base address can be DPTR or PC

       ORG 1000h

1000  mov a, #5

1002  movc a, @a + PC   ;a ß M[1008]

1003  Nop

• Table Lookup

• MOVC only can read internal code memory.

Conclusion: –

To be written by student.